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 74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs
March 1994 Revised November 1999
74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The ABT240 is an inverting octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density.
Features
s Output sink capability of 64 mA, source capability of 32 mA s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capability
Ordering Code:
Order Number 74ABT240CSC 74ABT240CSJ 74ABT240CMSA 74ABT240CMTC Package Number M20B M20D MSA20 MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names OE1, OE2 Description 3-STATE Output Enable Inputs I0-I7 O0-O7 Inputs Outputs
Truth Tables
Inputs OE1 L L H Inputs OE2 L L H
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
In L H X
Outputs (Pins 12, 14, 16, 18) H L Z Outputs (Pins 3, 5, 7, 9) H L Z
In L H X
(c) 1999 Fairchild Semiconductor Corporation
DS011664
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74ABT240
Absolute Maximum Ratings(Note 1)
Storage Temperature Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-Off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current (Across Comm Operating Range) Over Voltage Latchup (I/O) -150 mA 10V twice the rated IOL (mA) -0.5V to 5.5V -0.5V to VCC -65C to +150C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate (V/t) Data Input Enable Input 50 mV/ns 20 mV/ns -40C to +85C +4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID IOZH IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test 4.75 2.5 2.0 0.55 1 1 7 -1 -1 Min 2.0 0.8 -1.2 Typ Max Units V V V V V V A A A V A A mA A A A mA A mA mA A mA/ 0.1 MHz Max Max Min Min Min Min Max Max Max 0.0 VCC Conditions Recognized HIGH Signal Recognized LOW Signal IIN = -18 mA IOH = -3 mA IOH = -32 mA IOL = 64 mA VIN = 2.7V (Note 3) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 3) VIN = 0.0V IID = 1.9 A All Other Pins Grounded Output Leakage Current Output Leakage Current Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current -100 10 -10 -275 50 100 50 30 50 Outputs Enabled Outputs 3-STATE Outputs 3-STATE ICCD Dynamic ICC (Note 3) No Load 1.5 1.5 50 0 - 5.5V VOUT = 2.7V; OEn = 2.0V 0 - 5.5V VOUT = 0.5V; OEn = 2.0V Max Max 0.0 Max Max Max VOUT = 0.0V VOUT = VCC VOUT = 5.5V; All Others GND All Outputs HIGH All Outputs LOW OEn = VCC; All Others at VCC or Ground Additional ICC/Input VI = VCC - 2.1V Enable Input VI = VCC - 2.1V Data Input VI = VCC - 2.1V All Others at VCC or Ground Outputs Open OEn = GND, (Note 4) One Bit Toggling, 50% Duty Cycle
Note 3: Guaranteed, but not tested. Note 4: For 8 bits toggling, ICCD < 0.8 mA/MHz.
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74ABT240
AC Electrical Characteristics
TA = +25C VCC = +5V Symbol Parameter Min tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Data to Outputs Output Enable Time Output Disable Time 1.0 1.6 1.1 1.1 1.8 1.6 CL = 50 pF Typ Max 4.8 4.8 6.2 6.2 6.4 5.8 TA = -55C to +125C VCC = 4.5V-5.5V CL = 50 pF Min 0.8 1.0 0.8 0.8 1.0 1.0 Max 5.5 5.5 7.5 7.7 7.5 7.2 TA = -40C to +85C VCC = 4.5V-5.5V CL = 50 pF Min 1.0 1.6 1.1 1.1 1.8 1.6 Max 4.8 4.8 6.2 6.2 6.4 5.8 ns ns ns Units
Capacitance
Symbol CIN COUT (Note 5) Parameter Input Capacitance Output Capacitance Typ 5.0 9.0 Units pF pF VCC = 0V VCC = 5.0V Conditions TA = 25C
Note 5: COUT is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
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74ABT240
AC Loading
*Includes jig and probe capacitance
Standard AC Test Load Amplitude 3.0V
Test Input Signal Requirements
Test Input Signal Levels Rep. Rate 1 MHz tW 500 ns tr 2.5 ns tf 2.5 ns
AC Waveforms
Propagation Delay, Pulse Width Waveforms
Propagation Delay Waveforms for Inverting and Non-Inverting Functions
3-STATE Output HIGH and LOW Enable and Disable Times
Setup Time, Hold Time and Recovery Time Waveforms
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74ABT240
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body Package Number M20B
5
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74ABT240
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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6
74ABT240
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20
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74ABT240 Octal Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com


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